1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor device having a redundant row and a redundant column which can be accessed prior to substitution.
2. Description of the Background Art
A redundancy technology is known as a technology for improving manufacture yield of semiconductor memory devices. This redundancy technology is a technology by which a specific address is programmed to a redundancy circuit by blowing fuse elements of polycrystalline polysilicon formed on a semiconductor chip by laser beams or the like, so that a redundant memory cell is substituted for a normal memory cell.
With higher integration degree in recent years, however, a problem has been occurred that a manufactured semiconductor memory device cannot be repaired as an acceptable product since defects exist in a redundant memory cell to be substituted. As a method of solving such a problem, an example of a semiconductor memory device which can be subjected to pre-inspection of spare memory cells prior to repair processing is disclosed in U.S. Pat. No. 4,860,260.
FIG. 31 is a block diagram showing an arrangement of the semiconductor memory device disclosed in the document described above. Referring to FIG. 31, this semiconductor memory device includes a main body memory 1 having a plurality of memory cells; a row decoder 3 responsive to a row address AR for selecting one of word lines WL; a column decoder 5 responsive to a column address AC for selecting one of bit lines BL; a sense amplifier 6 for amplifying data read from main body memory 1; and an output buffer 7. This semiconductor memory device further includes a spare memory 2 having a plurality of spare memory cells; a spare decoder 40 responsive to spare row enable signals SPE1-SPE4 or test signals TEST1'-TEST4' for selecting one of spare memory word lines SWL; and a defect address sensing circuit 80 to which a substitute address can be programmed and for generating the spare row enable signals SPE1-SPE4 when a row address AR agrees with the programmed substitute address.
In a normal operation, row decoder 3 selects one of word lines WL in response to an externally applied row address AR. Thus, data is read from memory cells connected to the selected word line onto bit lines BL. Then, column decoder 5 selects one of bit lines BL in response to an externally applied column address AC. Thus, data on the selected bit line is amplified by sense amplifier 6, and is externally output through output buffer 7. In such a normal operation, defective address sensing circuit 80 is in an inactive state, and spare decoder 40 is also in an inactive state. Accordingly, spare memory word lines SWL are in a non-selection state.
On the other hand, in an access operation of spare memory cells, an address of a defective memory cell is pre-programmed to a basic circuit 81 having fuse elements. When such a defective address is sensed, spare row enable signals SPE1-SPE4 from basic circuit 81 attain H levels, so that spare decoder 40 is activated. At the same time, row decoder 3 is deactivated. The activated spare decoder 40 selects one of spare memory word lines SWL. Thus, data is read from spare memory cells connected to the selected spare memory word line SWL onto bit lines BL. Then, as in the case of a normal operation, column decoder 5 selects one of bit lines BL in response to an externally applied column address AC, and data on the selected bit line BL is amplified by sense amplifier 6 and is externally output through output buffer 7.
A method of inspecting spare memory 2 in this semiconductor memory device will now be described. FIG. 32 shows a test mode sensing circuit used in this semiconductor memory device. This test mode sensing circuit includes an input pad PD to which an address signal is applied, an inverter 36 for inverting a signal applied to input pad PD and supplying the inverted signal to an internal address buffer, and an inverter 37 for producing an internal test signal. Inverter 37 is constituted by a P channel MOS transistor 38 for loading and an N channel field transistor 39 for driving. Threshold voltage of N channel field transistor 39 is set to a value (about 9 V) higher than that of the power supply voltage Vcc.
FIG. 33 shows a test signal decoder circuit responsive to an internal test signal TEST and complementary signals A0, A0 and A1, A1 of row address signals for generating internal test signals TEST1'-TEST4'. Four spare memory word lines SWL1-SWL4 are selectively driven according to combinations of such four complementary signals A0, A0 and A1, A1.
FIG. 34 shows an arrangement of basic circuit 81 in FIG. 31. This basic circuit 81 includes a plurality of N channel MOS transistors 12-16 connected in parallel to each other, a plurality of fuse elements 18-22 each connected in series with a corresponding N channel MOS transistor, and a P channel MOS transistor 17 connected in common with these fuse elements 18-22.
In a test operation of the spare memory, voltage (for example, 10 V) higher than threshold voltage of N channel field transistor 39 is applied to input pad PD. Thus, an output signal (internal test signal TEST) of inverter 37 is rendered at a low potential. An inverted signal TEST thereof is applied to the test signal decoder circuit, so that one of test signals TEST1'-TEST4' is activated in response to address signals A0 and A1.
For example, in the case of (A0, A1)=(1, 1), a test signal TEST1' attains an H level and other test signals TEST2'-TEST4' are kept at L levels. Accordingly, one spare memory word line SWL1 is selected in response to such internal test signals TEST1'-TEST4'. In addition, normal row decoder 3 is deactivated in response to internal test signals TEST1'-TEST4'. An operation thereafter is similar to an operation in the case where a spare memory cell is accessed. Thus, according to such a semiconductor memory device, a spare memory cell can be tested without blowing fuse elements.
In the conventional semiconductor memory device described above, however, since one internal test signal is required for each OR gate 41 for selecting one spare memory word line, multiple signal lines are required. Accordingly, a large area for these signal lines is necessary, resulting in increase in chip size.
Furthermore, size of NOR gate 82 to which spare row enable signals SPE1-SPE4 and internal test signals TEST1'-TEST4' are applied increases. Even if NOR gate 82 is divided, the number of logic gates required increases with increase in the number of spare memory cells to be selected, resulting in increase in chip size.
Furthermore, in a semiconductor memory device (for example, a 16M bit dynamic RAM) having higher integration degree in recent years, since multiple spare memory cells are placed in a column direction as well as in a row direction, neither rows nor columns can be accessed simply prior to substitution in such an arrangement.
In particular, in the case where spare memory cells are provided in row and column directions, a spare memory cell located at an intersection of a redundant row and a redundant column must be tested in order to substitute a redundant row and a redundant column simultaneously, such a test cannot be performed according to such an arrangement.
In addition, in the test mode sensing circuit of FIG. 32, high voltage must continue to be applied to input pad PD for the whole period in a test mode of the spare memory. Therefore, input pad PD cannot use an address pin which is used for selecting a spare memory cell, and separate pads PD must be provided for spare memory cells.
If the above-described sensing circuit 80 is provided in each memory array block in a semiconductor memory device capable of performing a selective operation, a functional test for spare memory cells must be performed using an address for selecting a memory array block to be operated. Therefore, relationship between an address used for block selection and an address for a spare memory cell must be considered.